Apparatus and method for adjusting the substrate impedance of a MOS transistor

ABSTRACT

Method and apparatus for adjusting an impedance of a substrate of a Metal-Oxide-Semiconductor (MOS) transistor by providing a bias voltage and connecting a frequency-selective circuit between the substrate and the bias voltage. The frequency-selective circuit is also provided with at least one reactive element, such as an inductive element or a capacitive element, to obtain a certain frequency-response of the frequency-selective circuit and thus adjusts the substrate impedance of the MOS transistor. The method and apparatus are compatible with standard CMOS technology and applicable to RF switches, including T/R switches for processing high-frequency analog signals.

RELATED APPLICATIONS

This application claims priority from the provisional U.S. patentapplication No. 60/510,403, filed on 14 Oct. 2003 and incorporated asreference herein.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for improvingthe performance of a MOS transistor at select frequencies by adjustingthe transistor's substrate impedance with an impedance circuit thatemploys one or more reactive elements such as inductors and capacitors.

BACKGROUND OF THE INVENTION

Metal-Oxide-Semiconductor (MOS) transistors find extensive use in modernintegrated circuitry including chips fabricated with the standardComplementary Metal-Oxide-Semiconductor (CMOS) technology. Depending onthe operating conditions or modes of the integrated circuit, thesubstrate on which the transistors reside may require biasing. In thosesituations, the prior art teaches to apply a stable reference potentialalso referred to as DC bias to the substrate to control or enhance theoperation of the integrated circuit and/or its transistors. In anintegrated circuit, the substrate may be divided into regions that aredoped differently. Each region is known as a well or tub, and may haveone or more transistors. This is to provide electrical isolation betweentransistors in different wells. Each well of the substrate may be biasedto a different potential.

In the simplest case, the prior art teaches to apply a single DC bias orpotential to the substrate at all times. In other cases the prior artteaches selection of the DC potential depending on the change inoperation modes or other parameters of the integrated circuitry. Forexample, U.S. Pat. No. 6,031,411 to Tsay et al. teaches a bias circuitto provide a stable substrate reference potential for a variety ofoperating modes. More specifically, Tsay uses a control circuit toselect from among a plurality of substrate bias circuits only onesubstrate bias circuit to provide the substrate reference potential fora given operation mode. In U.S. Pat. No. 6,654,305 Tsunoda et al. teachto finely control power consumption of an Large Scale Integrated (LSI)system by using substrate-bias generation circuits for supplyingsubstrate biases independent of each other to functional modulesintegrated in the system. Tsunoda et al. use a substrate-bias controlcircuit for controlling the substrate-bias generation circuits. Inaddition, a storage unit is provided for storing control values to besupplied to the substrate-bias generation circuits. In U.S. Pat. No.6,124,752 Kuroda teaches an integrated circuit that biases thesemiconductor substrate to achieve power reduction in a stand-by modebased on threshold values. Still more methods and apparatus forcontrolling the substrate biases in accordance to operation modes of aprocessor are taught in U.S. Pat. No. 6,715,090 to Totsuka et al.

The above prior art references teach to apply one DC bias potential at atime to the substrate as a function of various performance parametersincluding operation mode and power consumption of an entire integratedcircuit or of a large portion or module thereof. In U.S. Pat. No.6,341,087 Kunikiyo teaches a semiconductor device with a body biasgeneration circuit that supplies a body region of an individual PMOStransistor with a body potential. The body potential is applied so thatthe body region may be reversely biased or not biased relative to thesource region in response to an input signal.

Although the above prior art solutions are useful in many situations,new wireless voice and data communication systems capable of deliveringmegabits of data at a fast rate pose a new set of challenges. A focus ofthe integrated circuit industry is now on developing highly-integrated,low-cost and low-power circuits for processing radio-frequency (RF)analog signals at frequencies in excess of 1 GHz. In such circuits,low-noise amplifiers (LNAs) and power amplifiers (PAs) tend to beintegrated on the same chip in the standard CMOS technology. To furtherincrease the integration level, transmit-receive (T/R) switches must beintegrated as well.

Unfortunately, performance parameters stand in the way of integratingT/R switches in CMOS circuits operating at high frequencies.Specifically, even with prior art substrate biasing solutions, MOStransistors in modern CMOS technology do not exhibit the linearity andloss performance at the desired frequencies to serve in T/R switches. Infact, the use of MOS transistors in CMOS technology for other low-lossand highly linear RF switches, e.g., RF switches for selectingcapacitors for tuning frequency selective circuits such asvoltage-controlled-oscillators (VCOs), is also compromised. Therefore,in the case of T/R switches for high-speed wireless applications, theprior art teaches the use of discrete components such as GaAsField-Effect Transistors (MESFETs) and PIN-type diodes.

Another factor limiting the performance of RF integrated circuits is thesubstrate resistance of the MOS transistor. In common practice, thesubstrate resistance of a MOS transistor is minimized to preventlatch-up and improve breakdown voltage. This is achieved by surroundingthe transistor with substrate contacts and strapping these with alow-resistance metal that is connected to a proper fixed voltage (suchas ground). However, in certain RF transceiver blocks, e.g., LNAs, it isdesirable to contemporaneously have as large a substrate resistance forthe cascade transistor as possible. Of course, maximizing substrateresistance in these blocks compromises the latch-up immunity predicatedon minimized substrate resistance. Furthermore, it is often difficult toincrease the substrate resistance of a MOS transistor due to technologyconstraints.

Hence, what is desired is a MOS transistor with substrate impedance thatcan be adjusted to match the performance requirements.

OBJECTS AND ADVANTAGES

In view of the shortcomings of the prior art, it is a primary object ofthe present invention to provide an apparatus and method for adjustingthe substrate impedance of a MOS transistor. In particular, it is anobject of the invention to provide an apparatus and method to adjust thesubstrate impedance of a MOS transistor in integrated circuits in CMOStechnology.

More specifically, it is an object to adjust the substrate impedance asnecessary for operating the MOS transistor at high frequencies whileexhibiting good performance including high linearity, low-loss, highlatch-up immunity and appropriate impedance at desired frequencies.

It is a further object of the invention to ensure improved performanceof MOS transistors in various switching applications including, amongother, RF switches and T/R switches.

These and numerous other objects and advantages of the present inventionwill become apparent upon reading the following description.

SUMMARY

In one embodiment the invention comprises a method for adjusting animpedance of a substrate, also referred to as substrate impedance, of aMetal-Oxide-Semiconductor (MOS) transistor. In accordance with themethod, a bias voltage is provided and a frequency-selective circuit isconnected between the substrate and the bias voltage. Thefrequency-selective circuit is also provided with at least one reactiveelement, such as an inductive element or a capacitive element, to obtaina certain frequency-response of the frequency-selective circuit. In thismanner, the frequency-response of the frequency-selective circuitadjusts the substrate impedance of the MOS transistor.

The present method of adjusting substrate impedance of MOS transistorsis well-suited for processing analog signals at high frequencies. Thus,the method can be used in radio-frequency (RF) switches includingtransmit-receive (T/R) switches for wireless communication circuits toprocess high-frequency signals at more than 1 GHz.

The reactive elements used in the frequency-selective circuit can beeither inductive elements or capacitive elements and they can beintegrated on-chip or positioned off-chip. In some embodiments only onereactive element, e.g., an inductive element is used. The inductiveelement can, in some cases, be a bond wire. In some embodiments onecapacitive and one inductive element are used. More specifically, insome of these embodiments the inductive element and the capacitiveelement are configured to form an LC-tank with a resonant frequency inan operating range of the MOS transistor.

The bias voltage applied to the frequency-selective circuit can be afixed at a certain value and it can be supplied by a fixed voltagesource. Note that the bias potential or bias voltage can be a groundvoltage.

The method of invention can include biasing of the MOS transistor. Forexample, in some embodiments a gate terminal or gate of the MOStransistor is biased.

The invention further extends to an apparatus for adjusting theimpedance of the MOS transistor's substrate. The apparatus has a biasvoltage source and a frequency selective circuit connected between thesubstrate and the bias voltage source. At least one reactive element,such as an inductive or a capacitive element, defines a certainfrequency-response of the frequency-selective circuit to thus adjust theimpedance of the substrate.

The apparatus of the invention can be used in MOS transistors instandard CMOS circuits. In particular, the present apparatus and methodcan be applied in RF switches, including T/R switches in integrated CMOST/R switches operating at above 1 GHz. A detailed description of theinvention and the preferred and alternative embodiments is presentedbelow in reference to the attached drawing figures.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a simplified circuit diagram of an apparatus according to theinvention with a frequency-selective circuit connected between thesubstrate and a fixed voltage source for adjusting the impedance of aMOS transistor's substrate.

FIG. 2 is a simplified circuit diagram of another embodiment of theapparatus employing an inductive element.

FIG. 3 is a simplified circuit diagram of yet another embodiment of theapparatus employing an LC-tank having an inductive element and acapacitive element.

DETAILED DESCRIPTION

The invention will be best understood by initially reviewing asimplified diagram of an apparatus 10 according to the invention asshown in FIG. 1. Apparatus 10 is designed for adjusting the impedance ofa Metal-Oxide-Semiconductor (MOS) transistor 12 built on a substrate 14.Transistor 12 has a source terminal 16, a gate terminal 18 and a drainterminal 20. It will be appreciated by a person skilled in the art thatin an integrated circuit, the substrate may be divided into regions thatare doped differently. Each region is known as a well or tub, and mayhave one or more transistors such as transistor 12. This architecture isdesigned to provide electrical isolation between transistors indifferent wells. Each well of the substrate may be biased to a differentpotential. Therefore, when referring to substrate 14 herein it is to beunderstood that substrate 14 may represent an entire substrate or just aportion or separate region thereof.

Apparatus 10 has a bias voltage source 22 for providing a bias voltageV_(bias). Bias voltage V_(bias), also known in the art as bias potentialor bias voltage potential, can be fixed at a certain value or it canvary. Source 22 can be a fixed source in embodiments where bias voltageV_(bias) is fixed. For example, in the present embodiment source 22 is aground contact and thus bias voltage V_(bias) is fixed at a groundvoltage or ground potential.

A frequency-selective circuit 24 is connected between substrate 14 andbias voltage source 22. Circuit 24 has a certain frequency-selectiveresponse over the operating range of transistor 12. In other words, theimpedance of circuit 24 varies as a function of frequency. Thefrequency-selective response of circuit 24 is selected with the aid ofat least one reactive element. Reactive elements include inductiveelements having certain inductances L or capacitive elements havingcertain capacitances C. A skilled artisan will appreciate that many waysof connecting inductive and capacitive elements in LC configurationsincluding serial and parallel are known in the art. Furthermore,appropriate selection of the configuration and the inductance L andcapacitance C values is used to produce a desired frequency-selectiveresponse.

The frequency-selective response of circuit 24 in the present embodimentis indicated by response graph 26. Specifically, response graph 26 plotsimpedance Z of circuit 24 as a function of frequency f. In an operatingrange 28 extending from a low frequency f_(l), to a high frequency f_(h)the impedance Z of circuit 24 has a low value Z_(l), while outsideoperating range 28 it has a high value Z_(h). Consequently, circuit 24adjusts the impedance of substrate 14 of transistor 12, or substrateimpedance, to Z_(l), within operating range 28 and to Z_(h) outsideoperating range 28. A person skilled in the art will recognize thatresponse graph 26 is merely exemplary and that a number of operatingranges with different values of impedance Z (and different shapes ofresponse graph 26) are possible.

The present method of adjusting substrate impedance of transistor 12 iswell-suited for processing analog signals at high frequencies. Thus, themethod of invention and apparatus 10 can be used in radio-frequency (RF)switches including transmit-receive (T/R) switches for wirelesscommunication circuits to process high-frequency signals at more than 1GHz.

In another apparatus 30 according to the invention, transistor 12 isconnected as shown in FIG. 2. In this embodiment transistor 12 is ann-type MOS transistor. A frequency-selective circuit 32 uses aninductive element or inductor 34 having an inductance L as the solereactive element to connect a substrate terminal 36 to a bias voltagesource 38. In the present case bias voltage source 38 is ground and thusthe bias voltage is the fixed ground voltage or V_(gnd).

A resistor 40 is used to bias a gate terminal 42 of transistor 12 to acontrol or switch voltage 44. Control voltage 44 is used for turningtransistor 12 on and off. Apparatus 30 can be employed in a T/R switchat radio-frequencies (RF), to achieve high linearity from a sourceterminal 46 to a drain terminal 48 of MOS transistor 12. The value ofinductance L of inductor 34 is chosen to exhibit a low value at directcurrent (dc) and low frequencies to enhance latch-up immunity. Inductor34 behaves as a high-impedance to any high-frequency signal applied asinput to transistor 12. Substrate terminal 36 is thus bootstrapped bysource or drain terminal 46 or 48 of MOS transistor 12. Gate terminal 42is also bootstrapped at high frequencies due to resistor 40, therebyresulting in a ‘floating’ MOS transistor 12 whose gate-source,gate-drain, source-substrate, and drain-substrate voltage amplitudes arerelatively small despite a large input voltage amplitude at source ordrain terminals 46, 48. In other words, the method of invention includesbiasing of MOS transistor 12. In this embodiment gate terminal 42 andthereby gate 18 of MOS transistor 12 is biased. The bias potential isselected to turn on or off transistor 12.

In another exemplary embodiment shown in FIG. 3, an apparatus 50 foradjusting the substrate impedance of transistor 12 has afrequency-selective circuit 52 that uses one inductive element 54 andone capacitive element 56. More specifically, inductive element 54 andcapacitive element 56 are configured to form an LC-tank 58 with aresonant frequency in an operating range of MOS transistor 12. In otherwords, inductor 54 and capacitor 56 are connected in parallel to biassubstrate terminal 36 of n-type MOS transistor 12 to a ground voltageV_(gnd).

A resistor 60 is used to bias gate terminal 42 of MOS transistor 12 to acontrol or switch voltage V_(switch) that turns transistor 12 on andoff. This embodiment permits transistor 12 to be used in a T/R typeswitch at RF, to achieve high linearity from the source terminal 46 todrain terminal 48. The inductance L and capacitance C values of inductor54 and capacitor 56 are chosen so that parallel LC-tank 58 resonates atthe input signal frequency of the T/R switch. The parallel resonancecreates a very high-impedance at the resonance frequency at substrateterminal 36. Substrate terminal 36 is thus bootstrapped by source ordrain terminal, 46 or 48, of MOS transistor 12. Gate terminal 42 is alsobootstrapped at the frequency of operation due to resistor 60, therebyresulting in a ‘floating’ MOS transistor whose gate-source, gate-drain,source-substrate, and drain-substrate voltage amplitudes are relativelysmall despite a large input signal amplitude at source or drainterminal, 46 or 48, of MOS transistor 12. LC-tank 58 behaves as alow-impedance at low frequencies and hence does not compromise thelatch-up immunity. A person skilled in the art will recognize manyadvantageous implementations of this technique, for example as describedin Niranjan A. Talwalkar, C. Patrick Yue, and S. Simon Wong, “AnIntegrated 5.2 GHz CMOS T/R Switch with LC-tuned Substrate Bias,”International Solid-State Circuits Conference, February 2003.

In FIG. 2 and FIG. 3 the source terminal 46 of MOS transistor 12 can beconnected to ground. This circuit can be used as a switch, e.g., toselect capacitors in and out of operation. Such an arrangement allows alow parasitic off-state capacitance from drain terminal 48 to groundwhile maintaining a low on-resistance. Since substrate terminal 36 isconnected to a very high-impedance due to inductor 34, or LC-tank 58, atthe frequencies of operation, the RF current from the drain, in theoff-state, flows through the two back-to-back diodes formed by thedrain-substrate and source-substrate diodes to the grounded source 16.This reduces the parasitic capacitance at the drain and greatly reducessubstrate loss because there is little RF current flowing in thesubstrate at the frequencies of operation.

In any of the above embodiments, the reactive elements used in thefrequency-selective circuit, whether they are inductive elements orcapacitive elements, can be integrated on-chip or positioned off-chip.The inductive element can, in some cases, be a bond wire. The apparatusof the invention can be used in MOS transistors in standard CMOScircuits.

It is understood that the examples and embodiments described herein arefor illustrative purposes only and that various modifications or changesin light thereof will be suggested to persons skilled in the art and areto be included within the spirit and purview of this application. Allpublications, patent applications cited herein are hereby incorporatedby reference for all purposes in their entirety.

In view of the above, it will be clear to one skilled in the art thatthe above embodiments may be altered in many ways without departing fromthe scope of the invention. Accordingly, the scope of the inventionshould be determined by the following claims and their legalequivalents.

1. A method for adjusting an impedance of a substrate of aMetal-Oxide-Semiconductor transistor, said method comprising: a)providing a bias voltage fixed at a predetermined value; b) connecting afrequency-selective circuit between said substrate and said biasvoltage; c) providing said frequency-selective circuit with at least onereactive element comprising at least one inductive element connecteddirectly between said substrate and said bias voltage, to obtain apredetermined frequency-response of said frequency-selective circuit,thereby adjusting said impedance.
 2. The method of claim 1, furthercomprising applying analog signals to said Metal-Oxide-Semiconductortransistor.
 3. The method of claim 1, further comprising applyinghigh-frequency signals to said Metal-Oxide- Semiconductor transistor. 4.The method of claim 1, wherein said at least one reactive elementfurther comprises at least one capacitive element.
 5. The method ofclaim 1, further comprising integrating at least one of said at leastone reactive element on-chip.
 6. The method of claim 1, furthercomprising positioning at least one of said at least one reactiveelement off-chip.
 7. The method of claim 1, wherein at least one of saidinductive elements is a bond wire.
 8. The method of claim 4, whereinsaid at least one reactive element comprises one inductive element andone capacitive element configured to form an LC-tank having a resonantfrequency in an operating range of said Metal-Oxide-Semiconductortransistor.
 9. The method of claim 1, wherein said bias voltage is aground voltage.
 10. The method of claim 1, further comprising biasing agate of said Metal-Oxide-Semiconductor transistor.
 11. An apparatus foradjusting an impedance of a substrate of a Metal-Oxide-Semiconductortransistor, said apparatus comprising: a) a fixed bias voltage source;b) a frequency-selective circuit connected between said substrate andsaid fixed bias voltage source; c) at least one reactive element in saidfrequency-selective circuit, said at least one reactive elementcomprising at least one inductive element connected directly betweensaid substrate and said fixed bias voltage for defining a predeterminedfrequency-response of said frequency-selective circuit, therebyadjusting said impedance.
 12. The apparatus of claim 11, wherein saidMetal-Oxide-Semiconductor transistor is integrated in a CMOS circuit.13. The apparatus of claim 11, wherein said at least one reactiveelement further comprises at least one capacitive element.
 14. Theapparatus of claim 11, wherein at least one of said at least onereactive element is integrated on-chip.
 15. The apparatus of claim 11,wherein at least one of said at least one reactive element is positionedoff-chip.
 16. The apparatus of claim 11, wherein at least one of saidinductive elements is a bond wire.
 17. The apparatus of claim 13,wherein said at least one reactive element comprises one inductiveelement and one capacitive element forming an LC-tank having a resonantfrequency in an operating range of said Metal-Oxide-Semiconductortransistor.
 18. The apparatus of claim 11, wherein said fixed biasvoltage source is a ground voltage.
 19. The apparatus of claim 11,further comprising a biasing circuit connected to a gate of saidMetal-Oxide-Semiconductor transistor.